With the increasing number of information to be processed, and the growing amount of data to be transmitted, fast switching of information becomes an important task in any communication network. The network nodes in which lines or transmission links are interconnected so that information may be exchanged between them are often causing delay in the network. It is therefore desirable to have switching nodes being fast and practically non-blocking. For the protocol adapters of such switching nodes, large and fast memories are required. In addition the management of these memories has to be fast, flexible, and very efficient to allow an adaptation of the system to different load situations.
The present invention relates mainly to communication networks with switching subsystems comprising a hardware implementation of the high speed buffer management according to this invention. The embodiments hereinafter described may be used as pad of a broadband switch for Gigabit local-area-networks, or for interconnecting supercomputers.
The nearest prior art is given by the article of A. P. Engbersen, "Algorithm For Managing Multiple First-In, First-Out Queues From A Single Shared Random-Access Memory", IBM Technical Disclosure Bulletin, Vol. 32, No. 3B, pp. 488-492, August 1989. A management technique for a plurality of queues in a single shared random-access memory (RAM) is given, which avoids the `garbage-collection` operation of re-organizing the fragmented memory required by known techniques. In this disclosure the queue elements are stored in this RAM, called data RAM, and a second RAM, called n.sub.-- part RAM, is used to store a pointer which indicates the locations of data in an output queue. The system works by having a register at every output port to indicate the address in the data RAM from which the next data is to be read. The register is updated whilst the data are being transmitted by reading, from the n.sub.-- part RAM at the same address as the address at which the data were stored in the data RAM, the address at which the next data in the output queue are stored. The hardware implementation of this technique is complex and not as fast as the present high speed management implementation, such that less clock cycles are necessary.